Embodiments of the present invention relate to a semiconductor device, and more particularly to a semiconductor device for substantially preventing a floating body from being generated, and a method for forming the same.
In recent times, the demand of memory devices of 40 nm or less has been rapidly increased to improve the integration degree. It is very difficult for a planar or recessed gate transistor for use in an 8F2 (F: minimum feature size) or 6F2 format to be scaled down to 40 nm or less. Therefore, the demand of a Dynamic Random Access Memory (DRAM) having a 4F2 cell structure which is capable of increasing the integration degree by 1.5˜2 times at the same scaling level has been rapidly increased. This increased demand has led to a vertical channel transistor to be newly proposed and developed.
The vertical channel transistor forms a surround-type gate electrode for enclosing the circumference of an active pillar vertically elongated on a semiconductor substrate, and forms a source region and a drain region at an upper part and a lower part of the pillar using the gate electrode as a reference, such that a channel is vertically formed. Accordingly, although the region of the vertical channel transistor is reduced, the effective channel length of the vertical channel transistor is not affected.
The vertical channel MOS transistor forms a gate electrode in the vicinity of the active pillar which is vertically elongated from a main surface of the semiconductor substrate, forms source/drain regions at upper and lower parts of the active pillar using the gate electrode as a reference point, such that a channel is formed perpendicular to the main surface of the semiconductor substrate. Therefore, although the area of the MOS transistor is reduced, the effective channel length of the vertical channel MOS transistor is not reduced. In order to implement the above-mentioned vertical channel semiconductor device, a new technology for forming a bit line which is buried in a device isolation region of a cell has recently been proposed.
The buried bit line according to the related art is formed by etching a semiconductor substrate by applying a self-alignment etching condition to a vertical pillar of the vertical channel semiconductor device and forming an insulation layer in the vicinity of the vertical pillar. The buried bit line formed by the above-mentioned method is in contact with a bit line contact formed by diffusion on one sidewall of the vertical pillar. The bit line contact is diffused as a line type on one sidewall of the vertical pillar, such that it causes a floating body phenomenon.
That is, because of the line-diffused bit line contact on one sidewall of the vertical pillar, a body voltage applied to a semiconductor substrate is not applied even to a channel part of the vertical transistor, such that a body portion for storing electric charges of the vertical transistor is floating. In more detail, an electric passage between the vertical transistor and the semiconductor substrate is blocked, such that it is difficult for a body bias to be applied to a channel of the vertical transistor. As a result, electric charges accumulate in the body of the vertical transistor and do not leak into the semiconductor substrate, such that the floating body effect is unavoidably encountered.